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| 6-BIT D REGISTER SY10E151 SY100E151 FEATURES s 1100MHz toggle frequency s Extended 100E VEE range of -4.2V to -5.46V s s s s Differential outputs Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E151 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as clocking control for the flip-flops. Data is clocked into the flip-flops on the rising edge of either CLK1 or CLK2 (or both). When both CLK1 and CLK2 are at a logic LOW, data enters the master and is transferred to the slave when either CLK1 or CLK2 (or both) go HIGH. The MR (Master Reset) signal operates asynchronously to make all Q outputs go to a logic LOW. BLOCK DIAGRAM D0 Q0 R D1 D R D2 D R D3 D R D4 D R D5 D R CLK1 CLK2 M R Q0 PIN CONFIGURATION MR CLK2 CLK1 NC VCCO Q5 Q5 18 17 D 25 24 23 22 21 20 19 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 D5 D4 D3 VEE D2 D1 D0 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Q4 Q4 VCC Q3 Q3 Q2 Q2 PLCC TOP VIEW J28-1 16 15 14 13 12 NC VCCO Q0 Q1 Q1 PIN NAMES Pin D0-D5 CLK1, CLK2 MR Q0-Q5 Q0-Q5 VCCO Function Data Inputs Clock Inputs Master Reset True Outputs Inverting Outputs VCC to Output VCCO Rev.: D Q0 Amendment: /0 1 Issue Date: November, 1998 Micrel SY10E151 SY100E151 TRUTH TABLES(1) Asynchronous Operation Inputs Dn X CLK1 X CLK2 X MR H Output Qn(t + 1) L Dn L H L H X X X Synchronous Operation Inputs CLK1 u u L L H u L CLK2 L L u u u H L MR L L L L L L L Output Qn(t + 1) L H L H Qn(t) Qn(t) Qn(t) NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care t = Time before positive CLK transition t+1 = Time after positive CLK transition u = LOW-to-HIGH transition DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 65 65 78 78 -- -- 65 65 78 78 -- -- 65 75 78 90 -- -- 150 TA = +25C -- -- 150 TA = +85C Max. 150 Unit A mA Condition -- -- -- -- Min. Typ. Max. Min. Typ. Max. Min. Typ. 2 Micrel SY10E151 SY100E151 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fMAX tPLH tPHL tS tH tRR tPW tskew tr tf Parameter Max. Toggle Frequency Propagation Delay to Output CLK MR Set-up Time, D Hold Time, D Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew Rise/Fall Time 20% to 80% 1100 1400 475 475 0 350 750 400 -- 300 650 650 -175 175 550 -- 65 450 -- 800 850 -- -- -- -- -- 700 TA = +25C 1100 1400 475 475 0 350 750 400 -- 300 650 650 -175 175 550 -- 65 450 -- 800 850 -- -- -- -- -- 700 TA = +85C Max. -- 800 850 -- -- -- -- -- 700 ps ps ps ps ps ps -- -- -- -- 1 -- Unit MHz ps 475 475 0 350 750 400 -- 300 650 650 -175 175 550 -- 65 450 Condition -- -- 1100 1400 Min. Typ. Max. Min. Typ. Max. Min. Typ. NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E151JC SY10E151JCTR SY100E151JC SY100E151JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 3 Micrel SY10E151 SY100E151 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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